1. Field of the Invention
The present invention regards a nonvolatile memory cell with high programming efficiency.
2. Description of the Related Art
As is known, flash memory cells are generally programmed by injecting channel hot electrons (channel hot electron programming, or CHE programming). However, this technique creates problems of scalability at supply voltages lower than 3.3 V on account of the drastic drop in injection efficiency when the applied voltage drops below the voltage corresponding to the barrier energy between silicon and silicon dioxide, which is 3.2 V.
To increase the injection efficiency, which constitutes a key parameter for obtaining a high writing speed (the so-called xe2x80x9cmemory bandwidthxe2x80x9d), it has been proposed to use a new injection method, known as channel-initiated substrate-electron (CHISEL) programming, which is described, for instance, in U.S. Pat. No. 5,659,504 published on Aug. 19, 1997 and U.S. Pat. No. 5,838,617 published on Nov. 17, 1998, both in the name of Bude et al. According to this method, during programming, a negative voltage is applied to the cell substrate. This voltage increases the injection of tertiary electrons, generated by impact ionization of secondary holes in turn generated by impact ionization by channel electrons. Thanks to the non-zero generation energy of the tertiary electrons and to the voltage drop between the substrate and the interface region close to the drain region, the injection of tertiary electrons, promoted by the application of the negative voltage to the substrate, completely dominates the injection process, and all the more, the smaller the drain voltage.
In a typical cell of a 0.3 xcexcm channel length technology, biased with a drain-to-source voltage Vds=4.5 V, and a source-to-body voltage Vsb=1 V, there are gate currents (injection current) Ig≅1-2 nA and hence writing speeds DVt/Dt≅1-2 V/s, with absorptions of drain current Ig≅50-150 xcexcA, corresponding to an injection efficiency Ig/Id of the order of 10xe2x88x925.
The above low injection efficiency is due to the fact that the injection process is intrinsically the fruit of three distinct cascaded processes, each of which typically has an efficiency much lower than unity; these are:
1) generation of secondary holes by channel electrons, injected by the source region and flowing towards the drain region;
2) generation of tertiary electrons deep within the substrate of the device by secondary holes in motion towards the substrate terminal;
3) heating of the tertiary electrons in motion towards the drain/substrate interface, and their injection into the floating gate region through the tunnel oxide.
There have moreover been proposed various cell structures which use in different ways the injection of tertiary electrons from the substrate in an attempt to increase the efficiency of the injection process. These structures are based on the integration of appropriate injectors of electrons in the substrate and in the collection of these charge carriers within the depleted region beneath the floating gate of the memory cell. The injectors may be formed by buried layers; see, for example, the erasing scheme for triple well DINOR cells (N. Tsuji et al., xe2x80x9cA New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characteristicsxe2x80x9d, Proc. IEDM, 1994, page 53) or else the VIPMOS cell (R. C. Wijburg et al., xe2x80x9cVIPMOS, A Novel Buried Injector Structure for EPROM Applicationsxe2x80x9d, Trans Electron Devices, 1991, vol. 38, No. 1, page 111), with writing obtained by punch-through from the buried pocket. Alternatively, the injectors can be formed by lateral bipolar transistors (see, for instance, B. Eitan et al., xe2x80x9cSubstrate Hot Electron Injection EPROMxe2x80x9d, Trans Electron Devices, 1984, vol. 31, No. 7, page 934).
The known solutions listed above present, however, one or more of the following considerable disadvantages:
1) low collection efficiency of the charge carriers injected by the depleted region formed beneath the floating gate region;
2) efficiency drop with the reduction of transistor size, in that the source and drain areas become a more important fraction of the total area of the device;
3) poor or no injection selectivity; consequently, during programming of a specific cell it is possible to disturb, i.e., program at least partially other cells of the array having the same substrate.
An embodiment of the invention provides a memory cell that is programmable in an efficient way.